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| TECHNICAL DATA IW4029B Presettable Up/Down Counter High-Voltage Silicon-Gate CMOS The IW4029B consists of a four-stage binary or BCD-decade up/down counter with provisions for look-ahead carry in both counting modes. The inputs consists of a single CLOCK, CARRY IN,(CLOCK ENABLE), BINARY/DECADE, UP/DOWN, PRESET ENABLE, and four individual JAM signals. Q1, Q2, Q3, Q4 and a CARRY OUT signal are provided as outputs. A high PRESET ENABLE signal allows information on the JAM INPUTS to preset the counter to any state asynchronously with the clock. A low on each JAM line, when the PRESET-ENABLE signal is high, resets the counter to its zero count. The counter is advanced one count at the positive transition of the clock when the CARRY IN and PRESET ENABLE signals are low. Advancement is inhibited when the CARRY IN or PRESET ENABLE signals are high. The CARRY OUT signal is normally high and goes low when the counter reaches its maximum count in the UP mode or the minimum count in the DOWN mode provided the CARRY IN signal is low. The CARRY IN signal in the low state can thus be considered a CLOCK ENABLE. The CARRY IN terminal must be connected to GND when not in use. Binary counting is accomplished when the BINARY/DECADE input is high; the counter counts in the decade mode when the BINARY/DECADE input is low. The counter counts up when the UP/DOWN input is high, and down when the UP/DOWN input is low. Parallel clocking provides synchronous control and hence faster response from all counting outputs. Ripple-clocking allows for longer clock input rise and fall times. * Operating Voltage Range: 3.0 to 18 V * Maximum input current of 1 A at 18 V over full packagetemperature range; 100 nA at 18 V and 25C * Noise margin (over full package temperature range): 1.0 V min @ 5.0 V supply 2.0 V min @ 10.0 V supply 2.5 V min @ 15.0 V supply ORDERING INFORMATION IW4029BN Plastic IW4029BD SOIC TA = -55 to 125 C for all packages PIN ASSIGNMENT LOGIC DIAGRAM PIN 16=VCC PIN 8= GND 64 IW4029B MAXIMUM RATINGS* Symbol VCC VIN VOUT IIN PD PD Tstg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Power Dissipation per Output Transistor Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +20 -0.5 to VCC +0.5 -0.5 to VCC +0.5 10 750 500 100 -65 to +150 260 Unit V V V mA mW mW C C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: : - 7 mW/C from 65 to 125C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Min 3.0 0 -55 Max 18 VCC +125 Unit V V C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 65 IW4029B DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) VCC Symbol VIH Parameter Minimum High-Level Input Voltage Test Conditions VOUT= 0.5 V or VCC - 0.5V VOUT= 1.0 V or VCC - 1.0 V VOUT= 1.5 V or VCC - 1.5V V 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 18 5.0 10 15 20 5.0 10 15 5.0 5.0 10 15 Guaranteed Limit -55C 3.5 7 11 1.5 3 4 4.95 9.95 14.95 0.05 0.05 0.05 0.1 5 10 20 100 0.64 1.6 4.2 -2 -0.64 -1.6 -4.2 25C 3.5 7 11 1.5 3 4 4.95 9.95 14.95 0.05 0.05 0.05 0.1 5 10 20 100 0.51 1.3 3.4 -1.6 -0.51 -1.3 -3.4 125 C 3.5 7 11 1.5 3 4 4.95 9.95 14.95 0.05 0.05 0.05 1.0 150 300 600 3000 0.36 0.9 2.4 mA -1.15 -0.36 -0.9 -2.4 Unit V VIL Maximum Low -Level VOUT= 0.5 V or VCC - 0.5V Input Voltage VOUT= 1.0 V or VCC - 1.0 V VOUT= 1.5 V or VCC - 1.5V Minimum High-Level Output Voltage Maximum Low-Level Output Voltage Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) VIN=GND or VCC V VOH V VOL VIN=GND or VCC V IIN ICC VIN= GND or VCC VIN= GND or VCC A A IOL Minimum Output Low VIN= GND or VCC (Sink) Current UOL=0.4 V UOL=0.5 V UOL=1.5 V Minimum Output VIN= GND or VCC High (Source) Current UOH=2.5 V UOH=4.6 V UOH=9.5 V UOH=13.5 V mA IOH 66 IW4029B AC ELECTRICAL CHARACTERISTICS(CL=50pF, RL=200k, Input tr=tf=20 ns) VCC Symbol tmax Parameter Maximum Clock Frequency (Figure 1) V 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 2 4 5.5 500 240 180 560 260 190 470 200 160 640 290 210 340 140 100 200 100 80 Guaranteed Limit -55C 25C 2 4 5.5 500 240 180 560 260 190 470 200 160 640 290 210 340 140 100 200 100 80 7.5 125C 1 2 2.75 1000 480 360 1120 520 380 940 400 320 1280 580 420 680 280 200 400 200 160 Unit MHz tPHL, tPLH Maximum Propagation Delay, Clock to Q (Figure 1) Maximum Propagation Delay, Clock to Carry Output (Figure 1) Maximum Propagation Delay, Preset Enable to Q (Figure 1) Maximum Propagation Delay, Preset Enable to Carry Output (Figure 1) Maximum Propagation Delay, Carry Input to Carry Output (Figure 1) Maximum Output Transition Time, Any Output (Figure 1) Maximum Input Capacitance ns tPHL, tPLH ns tPHL, tPLH ns tPHL, tPLH ns tPHL, tPLH ns tTHL, tTLH ns CIN pF FUNCTION TABLE CONTROL INPUT BIN/DEC (B/D) UP/DOWN (U/D) PRESET ENABLE (PE) CARRY IN (CI) (CLOCK ENABLE) LOGIC LEVEL H L H L H L H L ACTION BINARY COUNT DECADE COUNT UP COUNT DOWN COUNT JAM IN NO JAM NO COUNTER ADVANCE AT POS. CLOCK TRANSITION ADVANCE COUNTER AT POS. CLOCK TRANSITION 67 IW4029B TIMING REQUIREMENTS(CL=50pF, RL=200 k, Input tr=tf=20 ns) VCC Symbol tw Parameter Minimum Pulse Width, Clock (Figure 1) V 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 180 90 60 130 70 50 340 140 100 200 110 80 50 30 25 200 70 60 15 15 15 Guaranteed Limit -55C 25C 180 90 60 130 70 50 340 140 100 200 110 80 50 30 25 200 70 60 15 15 15 125C 360 180 120 260 140 100 680 280 200 400 220 160 100 60 50 400 140 120 30 30 30 Unit ns tw Minimum Pulse Width, Preset Enable (Figure 1) Minimum Setup Time, Clock to B/D or U/D (Figure 1) Minimum Removal Time, Preset Enable (Figure 1) Minimum Hold Time, Clock to Carry In (Figure 2) Minimum Setup Time, Carry In to Clock (Figure 1) Maximum Input Rise and Fall Times,Clock (Figure 2) ns tsu* ns trem* ns th** ns tsu ns tr, tf** s * ** From Up/Down, Binary/Decode, Carry In, or Preset Enable Control Inputs to Clock Edge. From Carry In to Clock Edge 68 IW4029B Figure 1. Switching Waveforms Figure 2. Switching Waveforms 69 IW4029B TIMING DIAGRAM; binary mode; J1=HIGH; J2=LOW; BIN/DEC=HIGH TIMING DIAGRAM; decade mode; J1=LOW; J4=LOW; BIN/DEC=LOW 70 IW4029B EXPANDED LOGIC DIAGRAM TRUTH TABLE CLOCK TE PE J X X L X X H X L H L H H L X H X X Q L Q H Q Q Q H Q L Q NC Q NC 71 |
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